The present application relates to the formation of copper interconnect structures for semiconductor devices and, more particularly to a method of protecting a copper seed layer from oxidation, agglomeration and corrosion during a queue time (Q-time) between copper deposition and copper plating.
Integrated circuits (ICs) commonly use copper interconnects to connect semiconductor devices such as, for example, transistors, on the ICs. These interconnects are typically formed using a damascene process in which a dielectric material layer is patterned to include at least one opening therein. Copper is subsequently deposited within the opening by electrochemical deposition and thereafter any copper that is located outside the opening can be removed via a planarization process. A copper seed layer is necessary to initiate the electrochemical deposition of copper. Because copper readily oxides when exposed to air, the Q-time (i.e., waiting time) between the copper seed layer deposition and the bulk copper electrochemical deposition has to be very short; otherwise, the copper seed layer may get oxidized, leading to corrosion and agglomeration of the copper in the seed layer. In addition, copper oxide readily dissolves in the plating solution, causing discontinuities in the copper seed layer. These discontinuities in the copper seed layer generate voids and/or plating defects in the copper layer plated over the copper seed layer, resulting in increased yield losses, device failures and reliability problems. Furthermore, the short Q-time makes on-product measurements of the copper seed layer impossible. Therefore, a method is needed to prevent oxidation of the copper seed layer and allow a longer Q-time between copper seed layer deposition and copper plating.